The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for the capacitor plates is conductively doped polysilicon. Such material is so utilized because of its compatibility with subsequent high temperature processing, good thermal expansion properties with SiO.sub.2, and its ability to be conformally deposited over widely varying topography.
As background, silicon occurs in crystalline and amorphous forms. Further, there are two basic types of crystalline silicon known as monocrystalline silicon and polycrystalline silicon. Polycrystalline silicon, polysilicon for short, is typically in situ or subsequently conductively doped to render the material conductive. Monocrystalline silicon is typically epitaxially grown from a silicon substrate. Silicon films deposited on dielectrics (such as SiO.sub.2 and Si.sub.3 N.sub.4) result in either an amorphous or polycrystalline phase. Specifically, it is generally known within the prior art that silicon deposited at wafer temperatures of less than approximately 580.degree. C. will result in an amorphous silicon layer, whereas silicon deposited at temperatures higher than about 580.degree. C. will result in a polycrystalline layer. The specific transition temperature depends on the source chemicals/precursors used for the deposition.
The prior art has recognized that capacitance of a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. Such roughness is typically transferred to the cell dielectric and overlying polysilicon layer interfaces, resulting in a larger surface area for the same planar area which is available for the capacitor. One procedure utilized to achieve surface roughening involves deposition under conditions which are intended to inherently induce a rough or rugged upper polysilicon surface. Such include low pressure chemical vapor deposition (LPCVD) techniques. Yet, such techniques are inherently unpredictable or inconsistent in the production of a rugged polysilicon film.
One type of polysilicon film which maximizes a roughened outer surface area is hemispherical grain (HSG) polysilicon typically provided to a thickness of from 300 Angstroms to 400 Angstroms. Such can be deposited or grown by a number of techniques. One technique includes direct LPCVD formation at 590.degree. C. Another includes formation by first depositing an amorphous silicon film at 550.degree. C using He diluted SiH.sub.4 (20%) gas at 1.0 Torr, followed by a dedicated subsequent high temperature transformation anneal.
One typical prior art process for providing a hemispherical grain layer of polysilicon for use as a capacitor electrode is described with reference to FIGS. 1-5. FIG. 1 illustrates a semiconductor wafer fragment 10 comprising a bulk monocrystalline silicon substrate 12 having a diffusion region 14 provided therein. An insulating dielectric layer 16 is provided over substrate 12, and having a contact opening 18 therethrough to diffusion region 14. A thin, substantially amorphous, silicon layer 20 is grown or otherwise provided outwardly of insulating layer 16 and within contact opening 18 in electrical connection with diffusion region 14.
Referring to FIG. 2, the temperature of the wafer is raised to a suitable annealing temperature to render layer 20 into a hemispherical grain layer 20a. The typical annealing temperature for producing layer 20a is 625.degree. C. Particle or other seeding can be provided outwardly of layer 20 prior to the annealing temperature to facilitate hemispherical grain growth.
Wafer fragment 10 is then typically transferred through ambient air to other suitable equipment for deposition of a desired capacitor dielectric layer outwardly of layer 20a. During the transfer of the wafer fragment to the dielectric layer deposition equipment, the temperature of the wafer is effectively lowered toward room ambient temperature. Subsequently, the wafer temperature is raised to the desired dielectric deposition temperature within the deposition equipment, which is higher than the hemispherical grain annealing temperature. This results in additional and undesired annealing of layer 20a. This additional annealing effectively smoothens the previously provided HSG layer, resulting in grain size expansion and overlap in producing the undesired smoother layer 20b of FIG. 3.
FIG. 4 illustrates subsequent Si.sub.3 N.sub.4 dielectric layer deposition. Subsequently, an outer capacitive plate or electrode would be provided. The resultant outer surface of layer 20b is thus undesirably smoother than layer 20a, thus reducing the desired increase in capacitance that would have been achieved by the surface roughening of the FIG. 2 step.
FIG. 5 illustrates the example prior art temperature vs. time profile that a wafer is subjected to in accordance with the above process. Cluster processing has been developed in the prior art, which enables transferring of wafers from one processing chamber to another without an intervening exposure of the wafers to ambient air conditions. Such can eliminate air exposure of wafers, and thermocycling between seeding and nitride growth all the way to room temperature. Regardless, the prior art still achieves hemispherical grain layer smoothing resulting from the increase in temperature from the HSG annealing temperature to the subsequent dielectric layer deposition temperature.
Accordingly, needs remain for providing improved methods of producing roughened conductively doped polysilicon films for utilization in improved capacitor constructions.